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Lattice® and Aldec®: Quick Timing Closure: Simulation and Debugging of Lattice Designs

The event was originally broadcast on:

Date: Wednesday, September 17, 2008
Time: 11:00 AM Pacific / 2:00 PM Eastern
Duration: 1 hour

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Overview

Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help you achieve timing closure faster. Don't make the same mistake - identify and address problems earlier using a simulator and STA tools in concert. This Webinar will use a Lattice reference design throughout, to show you how to use STA results to prepare a test bench, extract timing models from FPGA design tools, understand simulation results, and identify/trace problems before you program your Lattice FPGA. To wrap-up the verification process, designers can compare timing results against functional results to ensure design integrity.

Agenda

  1. About the Reference Design
  2. STA and Performance Evaluation
  3. Performing Timing Simulations
    1. Options for Generating HDL Timing Models
    2. Applying Standard Delay Format (SDF) Files
    3. Selecting a Set of Timing Delays
    4. Analyzing Results
  4. Tracing Timing Violations
  5. Comparing Timing Simulation against Functional Verification
    1. Waveform Comparison
    2. Testbench with Result Comparison

Speaker Information

Troy Scott

Troy Scott

 Troy Scott, Lattice Semiconductor

Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 15 years experience in the EDA and semiconductor industry. Troy's background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.
Jerry Kaczynski

Jerry Kaczynski

 Jerry Kaczynski, Aldec

Jerry Kaczynski has been employed at Aldec for 17 years and is currently in the position of Technical Marketing Engineer. Jerry has worked in the fields of HDL language and tool training, technical writing, application and research engineering. Jerry has participated in development of industry standards and has both working and teaching experience of PSL, VHDL, Verilog, SystemC and SystemVerilog.