CPLDs: Lattice Zero Power CPLDs

ispMACH 4000Z Zero Power CPLD Family

• Industry's Lowest Power CPLDs
• Standby Current Icc as low as 10µA

"Coolest Power, Coolest Price"

Based on Lattice's already popular ispMACH 4000 architecture, the ispMACH 4000Z family delivers both low static power and high speed. Devices operate from a 1.8V power supply providing low dynamic power. The 1.8-volt ispMACH 4000Z family supports a wide range of 3.3V, 2.5V and 1.8V I/O standards and features 5-volt tolerant I/Os when using the LVCMOS 3.3 interface. This family is available in commercial, industrial and automotive temperature ranges.

Lattice's ispMACH 4000Z family provides the low static power consumption, cost-effective logic implementation, flexible I/Os and power supply range demanded by handheld / portable applications.

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ispMACH 4000Z (1.8 V)

Device	Typical Standby Current (µA) (at 1.8 V, 25°C)	Density Macrocells	Speed		User I/O & Inputs	Packaging	Buy Now
			tPD	Fmax
4032ZC	10	32	3.5	267	32 + 4	48 TQFP
					32 + 4	56 csBGA
4064ZC	11	64	3.7	250	32 + 4	48 TQFP
					32 + 12	56 csBGA
					64 + 10	100 TQFP
					64 + 10	132 csBGA
4128ZC	12	128	4.2	220	64 + 10	100 TQFP
					96 + 4	132 csBGA
4256ZC	13	256	4.5	200	64 + 10	100 TQFP
					96 + 6	132 csBGA
					128 + 4	176 TQFP

Features

• Industry's Lowest Power Consumption
  • 10-13 µA stand-by current (Typical)
  • 18-23 µW power consumption (Typical)
• Coolest Power, Coolest Price
  • Priced below competitive standard power CPLDs
  • No premium for Zero Power!
• SuperFAST Performance
  • 3.5 ns tPD Pin-to-Pin Delay
  • 267 MHz System Performance
• Ease of Design
  • Excellent First-Time Fit and Refit Capability
  • 4 Global Clocks
  • 36 Inputs per Logic Block
  • Up to 80 Product Terms (PT) per Output
  • ORP for Pin Locking
  • Density Migration
  • Flexible Control, Clocking and OE
  • Fast, SpeedLocking^TM, and Wide PT Paths
• System Integration
  • Operation with 3.3V Supply (ispMACH 4000V) and operation with 1.8V Supply (ispMACH 4000Z)
  • 1.8V, 2.5V, 3.3V I/O Support
  • 5V tolerant I/O for LVCMOS 3.3 interface
  • Extended power supply operating range 1.6v to 1.9v
  • Automotive temperature range: -40 to +130°C Junction (T_j)
  • IEEE 1532 In-System Programmable (ISP^TM)
  • IEEE 1149.1 Boundary Scan Test
  • Open Drain Output for Flexible Bus Interface Capability
  • Programmable Pull-Up or Bus-Keeper Inputs
  • Hot Socketing Capability
  • 3.3V PCI Compatible
  • Programmable Output Slew Rate
  • Lead-free package option

ispMACH4000Z Evaluation Boards

The ispMACH4064Z Evaluation Board enables the user to program, evaluate, and de-bug a design for the Lattice ispMACH4064ZC device. Click the following links to learn more or order on-line:

ispMACH4000Z vs CoolRunner II

ispMACH 4000Z: Cooler than Xilinx CoolRunner II!

Compare the ispMACH 4000Z, Zero-Power Family from Lattice against the Xilinx CoolRunner II Family and discover the following:

• ispMACH 4000Z consumes significantly lower static current than Xilinx's CoolRunner II
• Xilinx CoolRunner II datasheet claims and specifications regarding static Icc are unspecified, potentially misleading, and/or missing

The table below shows the static Icc specification comparison between Lattice's ispMACH 4000Z and Xilinx's CoolRunner II. There are many specification "holes" to fall into in Xilinx's datasheet!

NOTES:

NS - No specification

All referenced Xilinx specifications are from datasheets available on the Xilinx website as of Aug-27-04.

Lattice WINS the ZERO-POWER CHALLENGE!