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ispMACH 4000ZE Ultra Low Power, Low Cost CPLD Family

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Based on Lattice’s popular low power ispMACH® 4000Z family architecture, the second-generation ispMACH 4000ZE is ideal for ultra low-power, high-volume portable applications. The ispMACH 4000ZE offers standby current as low as 10µA typical. The cost optimized and feature rich ispMACH 4000ZE devices offer ultra-small, space saving chip scale Ball Grid Array (csBGA) packages, a new Power Guard™ feature that enables ultra-low system power, and new system integration capabilities including an on-chip user oscillator and timer.

Built on proven E2CMOS® process technology, the ispMACH 4000ZE devices utilize a 1.8V core voltage and provides high levels of functionality and low system power. The ispMACH 4000ZE family supports LVCMOS and LVTTL 5.0, 3.3, 2.5, 1.8 and 1.5-volt outputs. Additionally, all inputs and I/Os are 5V tolerant.

Versions of the ispMACH 4000ZE family support both commercial and industrial temperature grades and are pin compatible with the prior zero power ispMACH 4000Z family in corresponding packages.

Family Member Selector Guide

ispMACH 4000ZE (1.8V)
Device Typical Standby
Current (µA)		 Density
Macrocells		 Speed User I/O
& Inputs		 Packaging
tPD Fmax
4032ZE 10 32 4.4 260 32 + 4 48 TQFP (7x7mm)
32 + 4 64 csBGA (5x5mm)
4064ZE 11 64 4.7 241 32 + 4 48 TQFP (7x7mm)
48 + 4
 64 csBGA (5x5mm)
64 + 10 100 TQFP (14x14mm)
64 + 10 144 csBGA (7x7mm)
4128ZE 12 128 5.8 190 64 + 10
 100 TQFP (14x14mm)
96 + 4 144 TQFP (20x20mm)
96 + 4 144 csBGA (7x7mm)
4256ZE 13 256 5.8 190 64 + 10 100 TQFP (14x14mm)
96 + 14
 144 TQFP (20x20mm)
108 + 4 144 csBGA (7x7mm)

Features New Space-Saving Packages for ispMACH

  • High Performance
    • fMAX = 260MHz maximum operating frequency
    • tPD=4.4ns Propagation delay
    • Up to four global clock pins with programmable clock polarity control
    • Up to 80 PTs per output
  • Ease of Design
    • Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
    • Up to four global OE controls
    • Individual local OE control per I/O pin
    • Excellent First-Time-Fit™ and refit
    • SpeedLocking™ Path and wide-PT path
    • Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
  • Ultra Low Power
    • Standby current as low as 10µA typical
    • 1.8V core; low dynamic power
    • Operational down to 1.6V VCC
    • Superior solution for power sensitive consumer applications
    • Per pin pull-up, pull-down or bus keeper control New! label
    • Power Guard with multiple enable signals New! label
  • Broad Device Offering
    • 32 to 256 macrocells
    • Multiple temperature range support
      • Commercial: 0 to 90°C junction (Tj)
      • Industrial: -40 to 105°C junction (Tj)
    • Space-saving packages
  • Easy System Integration
    • Operation with 3.3V, 2.5V, 1.8V, or 1.5V LVCMOS I/O
    • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
    • Hot-socketing support
    • Open-drain output options
    • Programmable output slew rate
    • 3.3V PCI compatible
    • I/O pins with fast setup path
    • Input hysteresis New! label
    • Operation with 1.8V supply
    • IEEE 1149.1 boundary scan testable
    • IEEE 1532 ISC compliant
    • 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP)
    • Pb-free package options (only)
    • On-chip user oscillator and timer New! label

ispMACH 4000ZE Evaluation Board

ispMACH 4000ZE Evaluation Board - thumbnailThe ispMACH 4000ZE Evaluation Board is designed to help you quickly evaluate the ispMACH 4000ZE, prototype your design, check performance and verify power consumption.