PCI Express Solutions

Ready to Use PCIe Portfolio

Lattice provides customers with low cost and low power programmable solutions that are ready-to-use right out of the box. For PCI Express a full suite of tested and interoperable solutions is available that includes:

• FPGAs with Embedded PCIe Compliant SERDES
• A Complete Portfolio of Soft and Hard IP Cores for PCI Express x1 and x4, and DMA
• Application Specific Development Kits, Evaluation Platforms and Reference Designs
• Test and Interoperability Reports for PMA Electrical Characterization and PCI-SIG Compliance Workshop

Silicon: Two Industry Leading Programmable PCIe Platforms

High Performance Analog SERDES PCI Express v1.1 compliant Ideal for long PCI Express based backplanes	Low Cost Digital SERDES PCI Express v1.1 compliant
Up to 32 Channels per Device Useful for multi-protocol bridging	Up to 16 Channels per Device Useful for multi-protocol bridging
Complete End-to-End Solution Rich PCS functionality flexiMAC and MACO LTSSM provide complete PHY and DL functionality in hard gates for x1 and x4 implementations Soft transaction available	Complete End to End Solution PIPE compliant PCS PCI Express x1 and x4 soft IP available
Very Low Power 105mW Per Channel Typical @ 3.125Gbps	Very Low Power 100mW Per Channel Typical @ 2.5Gbps)
Extreme Performance FPGA Fabric 500MHz block level performance	Low Cost FPGA Fabric High end features at low cost

Intellectual Property: Rich Portfolio of Soft and Hard IP

Lattice provides a comprehensive portfolio of soft and hard PCI Express IP, including DMA and Memory Controllers. By targeting the LatticeECP2M and LatticeSC/M platforms, developers will drastically reduce cost, power and footprint over competitive solutions.

Key

Development Kits

Our Development Kits combine application specific evaluation boards, evaluation PCI Express IP, relevant reference designs and host software and drivers in one comprehensive package. The Solution Kits allow a potential user to quickly and seamlessly evaluate the Lattice PCI Express Solutions portfolio, and to use it as a basis for customer specific PCI Express development.

Test and Interoperability

Lattice tests all critical components of the PCI Express stack rigorously, and puts a great deal of emphasis on interoperability with proven 3rd party silicon platforms. The following test documentation is available for customer review.

PMA Electrical Characterization

• TN1084 and Supplements (available under NDA) for PCI Express Transmit Jitter Specifications.
• We also perform additional testing for performance over PCI Express Cable using a Molex 28AWG Cable Assembly.

PCI SIG Testing:

Lattice is a regular participant of the PCI SIG and its Compliance Workshop programs. Testing is done on Lattice designed PCI Express End Point Add-in cards. All PCI Express End Point solutions have undergone rigorous testing and are currently compliant to Version 1.1 of the PCI Express specification. The following test are performed at the SIG:

• Electrical Testing – Examines device and card signal quality for eye pattern, jitter and bit error rate.
• Configuration Space Testing – Examines configuration space in the device by verification of required fields and values
• Link and Transaction Protocol Testing – Tests device behavior for link-level and transaction layer protocols.

• Download the test report

Interoperability

Lattice PCI Express solution undergo peer to peer compatibility tests with various motherboards and processors. These tests are held internally as well as at the PCI SIG Compliance Workshops. A total of 17 motherboards with a variety of processors have successfully interoperated with our PCI Express solutions.

• Download the interoperability report