 |
||
 New Account
Sign In
|
|
Too much information? Login or create an account to filter the news by your interests. NEW 2010-03-10 14:26:59.0 - White Paper: FPGAs have now matured into highly integrated devices that can include embedded ASIC-type functionality that provides enhanced interface capabilities. DSP processors and embedded memory coupled with soft microprocessor functionality means that the use of an FPGA in basestation design will provide the core of the functionality in a single reconfigurable chip. The advantages provided by programmable devices will enable faster time to market, with the flexibility to accommodate new and evolving standards cost effectively. NEW 2010-03-10 13:48:42.0 - White Paper: Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects where power equals cost. FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3's static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. NEW 2010-03-10 13:57:36.0 - White Paper: As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. DDR3 SDRAMs offer numerous advantages compared to DDR2. These devices are lower power, operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. This white paper examines the design challenges, and how the LatticeECP3 FPGA family, can facilitate DDR3 memory controller design. NEW 2010-03-10 13:57:36.0 - White Paper: As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. DDR3 SDRAMs offer numerous advantages compared to DDR2. These devices are lower power, operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. This white paper examines the design challenges, and how the LatticeECP3 FPGA family, can facilitate DDR3 memory controller design. NEW 2010-03-10 13:48:42.0 - White Paper: Power consumption is becoming an increasingly important variable when it comes to calculating OPEX and carbon footprint for telecom infrastructure projects where power equals cost. FPGAs are becoming one of the most important facets of basestation architectures, and so the spotlight has fallen on them to minimize power consumption. To minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors, and improved routing defaults and algorithms. As a result, the ECP3's static power consumption was reduced by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-capable FPGAs. NEW 2010-03-08 17:51:31.0 - New! SPI GPIO Expander, Reference Design RD1073 for MachXO and ispMACH 4000ZE. NEW 2010-03-08 17:51:31.0 - New! SPI GPIO Expander, Reference Design RD1073 for MachXO and ispMACH 4000ZE. NEW 2010-03-10 13:57:36.0 - White Paper: As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. DDR3 SDRAMs offer numerous advantages compared to DDR2. These devices are lower power, operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. This white paper examines the design challenges, and how the LatticeECP3 FPGA family, can facilitate DDR3 memory controller design. NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 14:26:59.0 - White Paper: FPGAs have now matured into highly integrated devices that can include embedded ASIC-type functionality that provides enhanced interface capabilities. DSP processors and embedded memory coupled with soft microprocessor functionality means that the use of an FPGA in basestation design will provide the core of the functionality in a single reconfigurable chip. The advantages provided by programmable devices will enable faster time to market, with the flexibility to accommodate new and evolving standards cost effectively. NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs NEW 2010-03-10 11:18:17.0 - White paper available: Embedded Display Control Using FPGAs |